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Logic synthesis
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#	Item
171	Magic: An Industrial-Strength Logic Optimization, Technology Mapping, and Formal Verification System Alan Mishchenko Niklas Een Robert Brayton Stephen Jang Maciej Ciesielski Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2010-03-19 22:25:46 Digital electronics Integrated circuits Standard cell Field-programmable gate array Logic optimization Retiming Physical design Logic synthesis Placement Electronic engineering Electronic design automation Electronic design
172	SmartOpt: An Industrial Strength Framework for Logic Synthesis Stephen Jang, Dennis Wu, Mark Jarvin Billy Chan, Kevin Chung Xilinx Inc. {sjang,wudenni,mjarvin,billy,kevinc}@xilinx.com Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2008-12-17 22:28:43 Digital electronics Integrated circuits Electronic design Field-programmable gate array Xilinx Logic synthesis Application-specific integrated circuit Placement Static timing analysis Electronic engineering Electronics Electronic design automation
173	Invariant-Strengthened Elimination of Dependent State Elements Michael L. Case1,2 Alan Mishchenko1 1 Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2008-05-19 21:42:19 Mathematics Electronics And-inverter graph Diagrams Retiming Invariant Logic synthesis Directed acyclic graph Functional dependency Electronic engineering Formal methods Electronic design automation
174	SNPS[removed]10-K Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2015-02-24 17:15:56 Integrated circuits Hardware verification languages Synopsys Hardware description language Electronic system-level design and verification Signoff Logic synthesis Integrated circuit design SystemVerilog Electronic engineering Electronic design automation Electronic design
175	Corporate Backgrounder Fall 2014 Synopsys Overview and History Synopsys, Inc. (Nasdaq:SNPS) provides products and services that accelerate innovation in the global electronics market. As a leader in electronic design Add to Reading List Source URL: www.synopsys.com Language: English Electronic design Hillsboro Oregon Synopsys Integrated circuits Signoff High-level synthesis Logic synthesis Xilinx Integrated circuit design Electronic engineering Electronic design automation Electronics
176	Logic Synthesis for Better Than Worst-case Designs Jason Cong1,2 and Kirill Minkovich1 1 Computer Science Department University of California, Los Angeles 2 Add to Reading List Source URL: cadlab.cs.ucla.edu Language: English - Date: 2009-03-09 16:24:15 Electronic design Integrated circuits Logic synthesis Algorithm Logic optimization Integrated circuit design Field-programmable gate array Application-specific integrated circuit Propagation delay Electronic engineering Electronics Digital electronics
177	CSEE E6861y Prof. Steven Nowick CSEE* E6861y Course Information Handout 1 Add to Reading List Source URL: www.cs.columbia.edu Language: English - Date: 2013-01-25 17:06:00 Electronic design Digital electronics Integrated circuits Logic synthesis Logic optimization Mathematical optimization Finite-state machine Integrated circuit design Circuit minimization Electronic engineering Electronics Electronic design automation
178	Introduction to Quartus II Software Introduction to Quartus II Software The Altera® Quartus® II design software is a multiplatform design environment that easily adapts to your specific needs in all phases of FPGA an Add to Reading List Source URL: www.altera.com Language: English - Date: 2011-05-03 16:48:08 Digital electronics Integrated circuits Altera Quartus Logic synthesis Altera VHDL Field-programmable gate array Static timing analysis Logic simulation Electronic engineering Electronic design automation Electronic design
179	A case study of FPGA mappers optimality Add to Reading List Source URL: cadlab.cs.ucla.edu Language: English - Date: 2007-02-12 14:27:19 Electronic design Digital electronics Integrated circuits Field-programmable gate array Logic synthesis Xilinx Logic optimization Application-specific integrated circuit Algorithm Electronic engineering Electronics Electronic design automation
180	Quartus II Incremental Compilation for Hierarchical and Team-Based Design Add to Reading List Source URL: www.altera.com Language: English - Date: 2014-08-12 19:20:20 Altera Quartus Netlist Field-programmable gate array Logic synthesis Design closure Disk partitioning Partition Altera Physical design Electronic engineering Electronic design automation Electronic design

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